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MDT1030
1. General Description
This ROM-Based 8-bit micro-controller uses a fully static CMOS design technology combines higher speed and smaller size with the low power and high noise immunity of CMOS. On chip memory system includes 2.0 K bytes of ROM, and 80 bytes of static RAM. u Power edge-detector Reset u Sleep Mode for power saving u 4 oscillator start-up time : 150 s, 20 ms, 40 ms, 80 ms u 8-bit real time clock/counter(RTCC) with 8-bit programmable prescaler u 4 types of oscillator can be selected by code options : RCLow cost RC oscillator LFXTLow frequency crystal oscillator XTALStandard crystal oscillator HFXTHigh frequency crystal oscillator u On-chip RC oscillator based Watchdog Timer(WDT) can be operated freely u Pull up resistors for the following pins : PA0~PA3, PB0~PB7, /MCLR, RTCC u Pull down resistors for the following pins : PA0~PA3, PB0~PB7, RTCC u 12 I/O pins with their own independent direction control
2. Features
The followings are some of the features on the hardware and software : u Fully CMOS static design u 8-bit data bus u On chip ROM size : 2.0 K words u Internal RAM size : 80 bytes (73 general purpose registers, 7 special registers) u 34 single word instructions u 12-bit instructions u 2-level stacks u Operating voltage : 2.3 V ~ 6.3 V u Operating frequency : 0 ~ 20 MHz u The most fast execution time is 200 ns under 20 MHz in all single cycle instructions except the branch instruction u Addressing modes include direct, indirect and relative addressing modes u Power-on Reset
3. Applications
The application areas of this MDT1030 range from appliance motor control and high speed automotive to low power remote transmitters/receivers, pointing devices, and telecommunications processors, such as Remote controller, small instruments, chargers, toy, automobile and PC peripheral ... etc.
This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw
P. 1
2005 /6
VER1.4
MDT1030
4. Pin Assignment
PA2 PA3 RTCC /MCLR Vss PB0 PB1 PB2 PB3 1 2 3 4 5 6 7 8 9 18 17 16 15 14 13 12 11 10 PA1 PA0 OSC1 OSC2 Vdd PB7 PB6 PB5 PB4
5. Pin Function Description
Pin Name PA0~PA3 PB0~PB7 RTCC /MCLR OSC1 OSC2 Vdd Vss I/O I/O I/O I I I O Function Description Port A, TTL input level Port B, TTL input level Real Time Clock/Counter, Schmitt Trigger input levels Master Clear, Schmitt Trigger input levels Oscillator Input Oscillator Output Power supply Ground
This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw
P. 2
2005 /6
VER1.4
MDT1030
6. Memory Map
(A) Register Map Address 00 01 02 03 04 05 06 07~0F 10~1F 30~3F 50~5F 70~7F Description Indirect Addressing Register RTCC PC STATUS MSR Port A Port B Internal RAM, General Purpose Register Internal Memory Select Register Internal Memory Select Register Internal Memory Select Register Internal Memory Select Register
(1) IAR ( Indirect Address Register) : R0 (2) RTCC (Real Time Counter/Counter Register) : R1 (3) PC (Program Counter) : R2
Write PC, CALL --- always 0 JUMP --- from instruction word RTWI, RET --- from STACK
A10
A9
A8
A7~A0
Write PC, JUMP, CALL --- from STATUS b6 b5 RTWI, RET --- from STACK
Write PC --- from ALU JUMP, CALL --- from instruction word RTWI, RET --- from STACK
This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw
P. 3
2005 /6
VER1.4
MDT1030
(4) STATUS (Status register) : R3 Bit 0 1 2 3 4 6X5 Symbol C HC Z PF TF page Carry bit Half Carry bit Zero bit Power loss Flag bit Time overflow Flag bit Page select bit : 00 : 000H --- 1FFH 01 : 200H --- 3FFH 10 : 400H --- 5FFH 11 : 600H --- 7FFH General purpose bit 7 XX Function
(5) MSR (Memory Select Register) : R4 Memory Select Register : 00 : 10~1F 01 : 30~3F 10 : 50~5F 11 : 70~7F
b7
b6
b5
b4
b3
b2
b1
b0
Read only "1" Indirect Addressing Mode (6) PORT A : R5 PA3~PA0, I/O Register (7) PORT B : R6 PB7~PB0, I/O Register
This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw
P. 4
2005 /6
VER1.4
MDT1030
(8) TMR (Time Mode Register) Bit Symbol Prescaler Value Function RTCC rate WDT rate 000 1:2 1:1 001 1:4 1:2 010 1:8 1:4 011 1 : 16 1:8 100 1 : 32 1 : 16 101 1 : 64 1 : 32 110 1 : 128 1 : 64 111 1 : 256 1 : 128 Prescaler assignment bit : 0 X RTCC 1 X Watchdog Timer RTCC signal Edge : 0 X Increment on low-to-high transition on RTCC pin 1 X Increment on high-to-low transition on RTCC pin RTCC signal set : 0 X Internal instruction cycle clock 1 X Transition on RTCC pin
2X0
PS2X0
3
PSC
4
TCE
5
TCS
(9) CPIO A, CPIO B (Control Port I/O Mode Register) The CPIO register is "write-only" x"0", I/O pin in output mode; x"1", I/O pin in input mode. (10) Configuration ROM : Bit 1 0 0 1 1 Bit 0 0 1 0 1 Oscillator Type RC Oscillator
LFXT Oscillator XTAL Oscillator HFXT Oscillator
Bit 3 0 0 1 1
Bit 2 0 1 0 1
Oscillator Start-up Time 150 s 20 ms 40 ms 80 ms
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P. 5
2005 /6
VER1.4
MDT1030
Bit 4 0 1 Watchdog Timer control Watchdog timer disable all the time Watchdog timer enable all the time
(B) Program Memory Address 000-7FF 7FF Program memory The starting address of the power on, external reset or WDT Description
7. Reset Condition for all Registers
Register CPIO A CPIO B TMR IAR RTCC PC STATUS MSR PORT A PORT B Address 00h 01h 02h 03h 04h 05h 06h Power-On Reset 1111 1111 1111 1111 --11 1111 xxxx xxxx 1111 1111 0001 1xxx 111x xxxx - - - - xxxx xxxx xxxx /MCLR or WDT Reset 1111 1111 1111 1111 --11 1111 uuuu uuuu 1111 1111 000# #uuu 111u uuuu - - - - uuuu uuuu uuuu
Note : uxunchanged, xxunknown, - xunimplemented, read as "0" #xvalue depends on the condition of the following table Condition /MCLR reset (not during SLEEP) /MCLR reset during SLEEP WDT reset (not during SLEEP) WDT reset during SLEEP Status: bit 4 u 1 0 0 Status: bit 3 u 0 1 0
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P. 6
2005 /6
VER1.4
MDT1030
8. Instruction Set
Instruction Code 010000 000000 010000 000001 010000 000010 010000 000011 010000 000100 010000 000rrr 010001 1rrrrr 011000 trrrrr 1110ii iiiiii 010111 trrrrr 011001 trrrrr 011010 trrrrr 011011 trrrrr 011100 trrrrr 011101 trrrrr 011110 trrrrr 010010 trrrrr 1101ii iiiiii 010011 trrrrr 1111 iiiiiiii 010100 trrrrr 1011 iiiiiiii 011111 trrrrr 010110 trrrrr Mnemonic Operands NOP CLRWT SLEEP TMODE RET CPIO STWR LDWI I R R Function No operation Clear Watchdog timer Sleep mode Load W to TMODE register Return Control I/O port register Store W to register Load register Load immediate to W Operating None 0/WT 0/WT, stop OSC W/TMODE Stack/PC W/CPIO W/R R/t I/W [R(0~3) R(4~7)]/t R + 1/t R + 1/t W + R/t R W/t (R+/W+1/t) R 1/t R 1/t R a W/t i a W/W R a W/t i a W/W R o W/t i o W/W /R/t R(n)/R(n-1), C/R(7), R(0)/C R(n)/r(n+1), C/R(0), R(7)/C 0/W 0/R 2005 /6 VER1.4 r TF, PF TF, PF None None None None Z None None Z None C, HC, Z C, HC, Z Z None Z Z Z Z Z Z Z C Status
LDR R, t
SWAPR R, t Swap halves register INCR R, t INCRSZ R, t Increment register
Increment register, skip if zero ADDWR R, t Add W and register SUBWR R, t Subtract W from register DECR R, t Decrement register DECRSZ R, t Decrement register, skip if zero ANDWR R, t AND W and register ANDWI IORWI i XORWI i RRR R, t i AND W and immediate Inclu. OR W and register Inclu. OR W and immediate Exclu. OR W and immediate Rotate right register IORWR R, t
XORWR R, t Exclu. OR W and register COMR R, t Complement register
010101 trrrrr
RLR
R, t
Rotate left register
C
010000 1xxxxx 010001 0rrrrr
CLRW CLRR R
Clear working register Clear register P. 7
Z Z
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MDT1030
Instruction Code 0000bb brrrrr 0010bb brrrrr 0001bb brrrrr 0011bb brrrrr 1100 nnnnnnnn 1010ii iiiiii 100n nnnnnnnn Note : W : WT : TMODE : CPIO : TF : PF : PC : OSC : Inclu. : Exclu. : AND : Mnemonic Operands BCR BSR R, b R, b Bit clear Bit set Bit Test, skip if clear Bit Test, skip if set Call subroutine Function Operating 0/R(b) 1/R(b) Skip if R(b)=0 Skip if R(b)=1 n/PC, PC+1/Stack Status None None None None None None None
BTSC R, b BTSS R, b CALL RTWI JUMP i n n
Return, place immediate to W Stack/PC, i/W JUMP to address b t : : 0 1 R: C: HC : Z: / : x : i : n: n/PC
Working register Watchdog timer TMODE mode register Control I/O port register Timer overflow flag Power loss flag Program Counter Oscillator Inclusive ` a' Exclusive ` o' Logic AND ` a'
Bit position Target : Working register : General register General register address Carry flag Half carry Zero flag Complement Don't care Immediate data ( 8 bits ) Immediate address
9. Electrical Characteristics
(A) Operating Voltage & Frequency Vdd
R
2.3 V ~ 6.3 V
FrequencyR Hz ~ 20 MHz 0
(B) Input Voltage : @ V ddx 5.0 V, Temperaturex25 J Port Vil Vih PA, PB RTCC, /MCLR PA, PB Min. Vss Vss 2.0 V 3.4 V Max. 1.0 V 0.8 V Vdd Vdd
RTCC, /MCLR Threshold Voltage :
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P. 8
2005 /6
VER1.4
MDT1030
Port A, Port B V thx 1.56 V RTCC, /MCLR V il x 1.4 V, V ih x 2.9 V (Schmitt Trigger) (C) Output Voltage : @ V ddx 5.0 V, Temperaturex25 J, the typical value as followings : PA, PB Port Iohx 20.0 mA Iol x 20.0 mA Iohx 5.0 mA Iol x 5.0 mA (D) Leakage Current @ V ddx 5.0 V, Temperaturex25 J, the typical value as followings : Iil Iih (E) Sleep Current @WDTDisable, Temperaturex25 J Vddx 2.3 ~ 6.3 V, ddO 1.0 A I @WDTEnable, Temperaturex25 J, the typical value as followings : Vddx 2.3 V Vddx 3.0 V Vddx 4.0 V Vddx 5.0 V Vddx 6.3 V IddO 1.0 A Iddx 2.0 A Iddx 5.0 A Iddx 12.0 A Iddx 20.0 A 1.0 A (Max.) I 1.0 A (Max.) Vohx 3.50 V Vol x 0.44 V Vohx 4.70 V Vol x 0.20 V
(F) Operating Current / Voltage Temperaturex25 J, the typical value as followings :
This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw
P. 9
2005 /6
VER1.4
MDT1030
(i) OSC TypexRC ; WDTEnable; @ V ddx 5.0 V Cext. (F) Rext. (Ohm) 4.7 K 10.0 K 3P 47.0 K 100.0 K 300.0 K 470.0 K 4.7 K 10.0 K 20P 47.0 K 100.0 K 300.0 K 470.0 K 4.7 K 10.0 K 100P 47.0 K 100.0 K 300.0 K 470.0 K 4.7 K 10.0 K 300P 47.0 K 100.0 K 300.0 K 470.0 K Frequency (Hz) 12.4 M 7.0 M 1.7 M 842.0 K 282.5 K 180.0 K 5.40 M 2.80 M 666.6 K 318.2 K 106.5 K 68.8 K 1.66 M 851.0 K 193.5 K 92.6 K 29.8 K 18.7 K 695.0 K 350.0 K 79.1 K 35.5 K 11.9 K 7.5 K Current (A) 1.9 m 1.1 m 310.0 180.0 90.0 75.0 900.0 500.0 150.0 100.0 70.0 60.0 320.0 180.0 80.0 65.0 60.0 55.0 160.0 105.0 65.0 60.0 55.0 53.0
This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw
P. 10
2005 /6
VER1.4
MDT1030
(ii) OSC TypexLF (C=20 p); WDTEnable Voltage/Frequency 2.3 V 3.0 V 4.0 V 5.0 V 6.3 V 32 K 4.0 A 8.0 A 17.0 A 30.0 A 58.0 A 455 K X 50.0 A 70.0 A 110.0 A 160.0 A 1M X 85.0 A 140.0 A 200.0 A 290.0 A Sleep O1.0 A 2.0 A 4.0 A 12.0 A 20.0 A
(iii) OSC TypexXT (C=10 p); WDTEnable Voltage/Frequency 2.1 V 3.0 V 4.0 V 5.0 V 6.3 V 1M 65.0 A 120.0 A 210.0 A 330.0 A 530.0 A 4M 220.0 A 365.0 A 550.0 A 750.0 A 1.2 mA 10 M 490.00 A 800.00 A 1.20 mA 1.70 mA 2.40 mA Sleep O1.0 A 2.0 A 4.0 A 12.0 A 20.0 A
(iv) OSC TypexHF (C=10 p); WDTEnable Voltage/Frequency 2.1 V 3.0 V 4.0 V 5.0 V 6.3 V (G) Pull Resistance @ Input Mode : V ddx 3.0 V PORT RTCC /MCLR Pull-High Pull-Low Pull-High Pull-Low Pull-High Resistance Resistance Resistance Resistance Resistance R x 330.0 KOhm hi R x 330.0 KOhm lo R x 300.0 KOhm hi R x 300.0 KOhm lo R x 300.0 KOhm hi 4M 220.0 A 400.0 A 640.0 A 900.0 A 1.4 mA 10 M 560.00 A 900.00 A 1.60 mA 2.40 mA 3.60 mA 20 M 950.00 A 1.50 mA 2.60 mA 3.70 mA 5.50 mA Sleep O1.0 A 2.0 A 4.0 A 12.0 A 20.0 A
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P. 11
2005 /6
VER1.4
MDT1030
@ Input Mode : V ddx 5.0 V PORT RTCC /MCLR Pull-High Pull-Low Pull-High Pull-Low Pull-High Resistance Resistance Resistance Resistance Resistance R x 160.0 KOhm hi R x 160.0 KOhm lo R x 150.0 KOhm hi R x 150.0 KOhm lo R x 150.0 KOhm hi
p.s. : It is only a reference value for the Pull High/Low Resistance, and the accurate value of the Resistance depends on the various parameter of the Process. But the variation of the value will be not more than 20%. (H) Power Edge-detector Reset Voltage, @ V ddx 5.0 V VprO 1.1~1.3 V Vpr
R
Vdd (Power Supply)
The Power Edge-detector function can be chosen as either "Enable" or "Disable" : (i) "Disable" condition : No Power EDT function. (ii) "Enable" condition : Under operation condition(Not in Sleep Mode), if the operating voltage(V pr) was not dropped down smoothly, then, 1.1 VOVprO 2.0 V, the IC will be reset.
This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw
P. 12
2005 /6
VER1.4
MDT1030
(I) The basic WDT time-out cycle time Temperaturex25 J, the typical value as followings : Voltage (V) 2.3 3.0 4.0 5.0 6.3 Basic WDT time-out cycle time (ms) 28.90 25.60 22.30 20.00 18.10
10. Port A and Port B Equivalent Circuit
Working Register
D QB
Data I/P
I/O Control
CK
I/O Control Latch
Q
MOS Pull-Hi (Long Channel)
Information Sheet Pull Hi/Lo Selection
Port I/O Pin
D
Write
CK
Data O/P Latch
Q
MOS Pull-Down (Long Channel)
Data Bus
QB D
Read
Data I/P Latch
CK
Input Resistor TTL Input Level
This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw
P. 13
2005 /6
VER1.4
MDT1030
11. M CLRB and RTCC Input Equivalent Circuit
MOS Pull Hi (Long Channel)
R U 1 K
MCLRB Schmitt Trigger
Information Sheet Pull Hi/Lo Selection
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P. 14
2005 /6
VER1.4
MDT1030
MOS Pull Hi (Long Channel)
R U 1 K
RTCC Schmitt Trigger
MOS Pull Low (Long Channel)
Information Sheet Pull Hi/Lo Selection
This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw
P. 15
2005 /6
VER1.4
MDT1030
12. Block Diagram
Stack Two Levels
ROM 2048N12
RAM 73N8 Port A
Port PA0~PA3 4 bits
11 bits 11 bits 12 bits
Program Counters
Instruction Register
Special Register
D0~D7 OSC1 OSC2 MCLR
Port B Instruction Decoder
Port PB0~PB7 8 bits
Oscillator Circuit
Control Circuit
Data 8-bit
Power on Reset Power Down Reset Working Register ALU Status Register
8-bit Timer/Counter
Prescale
WDT/OST Timer
RTCC
This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw
P. 16
2005 /6
VER1.4
MDT1030
13. Capacitor Selection For Crystal Oscillator
(a) With built-in Oscillation Capacitors ( Default for HF,XT,LF ) @ Vddx 2.3V~5.5 V , C1=C2=10P~15P
This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw
P. 17
2005 /6
VER1.4
MDT1030
(b) Without built-in Oscillation Capacitors @ Vddx 3.0 V~ 5.0 V Osc. Type Resonator Freq. 20 MHz HF 10 MHz 4 MHz 10 MHz XT 4 MHz 1 MHz 1 MHz LF 455 K 32 K C1 5 pF ~10 pF 10 pF ~50 pF 10 pF ~50 pF 10 pF ~30 pF 10 pF ~50 pF 10 pF ~30 pF 3 pF ~5 pF 10 pF ~30 pF 10 pF ~20 pF C2 10 pF~30 pF 20 pF ~100 pF 20 pF ~100 pF 10 pF ~50 pF 20 pF ~100 pF 20 pF ~50 pF 3 pF ~5 pF 20 pF ~50 pF 15 pF ~30 pF
This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw
P. 18
2005 /6
VER1.4
MDT1030
To increase the stability of oscillator and the ability of anti-noise, the above values of the external capacitor range are recommended, but the higher capacitance will increase the start-up time. There do not have built-in Oscillation Capacitors for RC type.
This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw
P. 19
2005 /6
VER1.4

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